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DS1384 Watchdog Timekeeping Controller
www.maxim-ic.com
FEATURES
Keeps Track of Hundredths of Seconds, Seconds, Minutes, Hours, Days, Date of the Month, Months, and Years with Leap Year Compensation Valid Up to 2100 Watchdog Timer Restarts an Out-ofControl Processor Alarm Function Schedules Real-Time Related Activities Programmable Interrupts and SquareWave Outputs Bytewide RAM-Like Access 50 Bytes of On-Board User RAM Greater Than 10 Years Timekeeping and Data Retention in the Absence of Power with Small Lithium Coin Cells Supports Up to 128k x 8 of External Static RAM All Timekeeping Registers and On-Board RAM are Individually Addressable via the Address and Data Bus
PIN CONFIGURATION
TOP VIEW GND X1 X2 GND A16 INTA VCC VCCO SQW PFO VBAT2 44 1 INTB/(INTB) N.C. A14 A12 A7 A6 A5 A4 A3 A2 A1 11 12 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 34 33
DS1384
23 22 CEO
A15 VBAT1 WE A13 A8 A9 A11 OE A10 CE OE
MQFP
ORDERING INFORMATION
PART DS1384FP-12 DS1384FP-12+ TEMP RANGE 0C to +70C 0C to +70C VOLTAGE (V) 5.0 5.0 PIN-PACKAGE 44 MQFP 44 MQFP TOP MARK* DS1384FP DS1384FP
+ Denotes lead-free/RoHS-compliant device. * A "+" anywhere on the top mark indicates a lead-free/RoHS-compliant device.
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REV: 112105
DS1384
DETAILED DESCRIPTION
The DS1384 watchdog timekeeping controller is a self-contained real-time clock, alarm, watchdog timer, and interval timer that provides control of up to 128k x 8 of external low-power CMOS static RAM in a 44-pin quad flat-pack package. An external crystal and battery are the only components required to maintain time of day and RAM memory contents in the absence of power. Access to all RTC functions and the external RAM is the same as conventional bytewide SRAM. Data is maintained in the watchdog timekeeper by intelligent control circuitry, which detects the status of VCC and write protects both memory and timekeeping functions when VCC is out of tolerance. Timekeeper information includes hundredths of seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap year. The timekeeper operates in either 12- or 24-hour format with an AM/PM indicator. The watchdog internal timer provides watchdog alarm windows and interval timing between 0.01 seconds and 99.99 seconds. The real time alarm provides for preset times of up to one week. All the RTC functions and the internal 50 bytes of RAM reside in the lower 64 bytes of the attached RAM memory map. The externally attached static RAM is controlled by the DS1384 via the OER and CEO signals. Automatic backup and write protection for an external SRAM is provided through the VCCO, CEO, and OER pins. The lithium energy source used to permanently power the real time clock is also used to retain RAM data in the absence of VCC power through the VCCO pin. The chip enable output to RAM (CEO) and the output enable to RAM (OER) are controlled during power transients to prevent data corruption. The DS1384 is a complete one-chip solution in that an external crystal and battery are the only components required to maintain time of day memory status in the absence of power.
PIN DESCRIPTION
PIN NAME FUNCTION Interrupt Output B (Active High or Low). INTB outputs the alarm (time of day or watchdog) that is not selected for INTA. This pin is programmable high or low. Both INTA and INTB/(INTB) are opendrain outputs. The two interrupts and the internal clock continue to run regardless of the VCC level. However, it is important to ensure that the pullup resistors used with the interrupt pins are never pulled up to a value that is greater than VCC + 0.3V. As VCC falls below approximately 3.0V, a power-switching circuit turns the lithium energy source on to maintain the clock and timer data functionality. It is also required to ensure that during this time (battery-backup mode) the voltage present at INTA and INTB/(INTB) never exceeds VBAT. At all times the current on each should not exceed +2.1mA or -1.0mA. No Connection Address Bus (Input). The address bus inputs qualified by CE, OE, WE, and VCC are used to select the on-chip 64 timekeeping/RAM registers within the memory map of the external SRAM controlled as nonvolatile storage. When the qualified address bus value is within the range of 00000H-0003FH, one of the internal registers is selected and OER remains inactive. When the value is outside the range, OE is passed through to OER.
1
INTB/(INTB)
2 3 4 5-12 25 27 28 29 30 33 40
N.C. A14 A12 A7-A0 A10 A11 A9 A8 A13 A15 A16
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PIN 13, 14, 15, 17-21 16, 41, 44 22
NAME DQ0, DQ1, DQ2, DQ3-DQ7 GND CEO
23
OER
24
CE
26
OE
31
WE
32, 34
VBAT1, VBAT2
35 36
PFO SQW
37
VCCO
FUNCTION Data Bus (Bidirectional). When a qualified address from 00000H- 0003FH is presented to the device, data is passed to or from the onchip 64 timekeeping/RAM registers via the data bus lines. Data is written on the rising edge of WE when CE is active. If CE is active without WE, data is read from the device and driven onto the data bus pins when OE is low. Ground. DC power input. Active-Low RAM Chip-Enable Output. When power is good, the CE input is passed through to CEO. If VCC is below VPF, CEO remains at an inactive high level. Active-Low RAM Output Enable (Output). When power is good and the address value is not within the range of 00000H and 0003FH, and CE is active, the OE input is passed through to OER. If these conditions are not met, OER remains at an inactive high level. Active-Low Chip Enable (Input). This signal must be asserted low during a bus cycle to access the on-chip timekeeping RAM registers, or to access the external RAM via CEO. Active-Low Output Enable (Input). This signal identifies the time period when either the RTC or the external SRAM drives the bus with read data, provided that CE is valid with WE disabled. When one of the 64 on-chip registers is selected during a read cycle, the OE is the enable signal for the DS1384 output buffers and the data bus is driven with read data. When the external RAM is selected during a read cycle, the OE signal is passed through to the OER pin so that read data is driven by the external SRAM. Active-Low Write Enable (Input). This signal identifies the time period during which data is written to either the on-chip registers or to an external SRAM location. When one of the on-chip 64 registers is addressed, data is written to the selected register on the rising edge of WE. Battery Inputs for Any Standard 3V Lithium Cell or Other Energy Source. Battery voltage must be held between 2.4V and 4V for proper operation. In the absence of power, the DS1384 has a maximum load of 0.5A at +25C. This should be added to the amount of current drawn from the external RAM in standby mode at +25C to size the external energy source. The DS1384 samples VBAT1 and VBAT2 and always selects the battery with the higher voltage. If only one battery is used, the unused battery input must be grounded. Power-Fail Signal (Output, Active Low when VWP Occurs). High state occurs tREC after power-up and VCC 4.5V. Square-Wave Output. This pin can be programmed to output a 1024Hz square-wave signal. When the signal is turned off, the pin is high impedance. Switched DC Power for SRAM (Output). This pin is connected to VCC when VCC voltage is above VSO (the greater of VBAT1 or VBAT2). When VCC voltage falls below this level, VCCO is connected to the higher voltage battery pin.
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PIN 38 39
NAME VCC INTA
42, 43
X1, X2
FUNCTION DC Power Input. DC operating voltage is provided to the device on this pin. VCC is the +5V input. Active-Low Interrupt Output A. INTA can be programmed as a timeof-day alarm or as a watchdog alarm. (INTB becomes the alternate function). INTA can also be programmed to output either a pulse or a level. Connections for Standard 32.768kHz Quartz Crystal. When ordering, request a load capacitance (CL) of 6pF. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real Time Clocks.
ADDRESS DECODING
The DS1384 accommodates 17 address lines, which allows direct connection of up to 128k bytes of static RAM. The lower 14 bytes of RAM, regardless of the density used, will always contain the timekeeping, alarm, and watchdog registers. The 14 clock registers reside in the lower 14 RAM locations without conflict by inhibiting the OER (output enable RAM) signal during clock access. Since the watchdog timekeeping chip actually contains 64 registers (14 RTC and 50 user RAM), the lower 64 bytes of any attached memory resides within the DS1384. However, the RAM's physical location is transparent to the user and the memory map looks continuous from the first clock address to the upper most attached RAM address.
OPERATION--READ CYCLE
The DS1384 executes a read cycle whenever WE is inactive (high) and CE and OE are active (low). The unique address specified by the address inputs (A0-A16) defines which of the on-chip 64 RTC/RAM or external SRAM locations is to be accessed. When the address value presented to the DS1384 is in the range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and valid data will be available to the eight data output drivers within tACC (access time) after the address input signal is stable, providing that the CE and OE access times are also satisfied. If they are not, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE for OE rather than the address access time. When one of the on-chip registers is selected for read, the OER signal will remain inactive throughout the read cycle. When the address value presented to the DS1384 is in the range of 00040H through 1FFFFH, an external SRAM location will be selected. In this case the OE signal will be passed to the OER pin, with the specified delay times of tAOEL or tOERL.
OPERATION--WRITE CYCLE
The DS1384 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in the active (low) state after the address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery state (tWR) before another cycle can be initiated. Data must be valid on the data bus with sufficient Data Set Up (tDS) and Data Hold Time (tDH) with respect to the earlier rising edge of CE or WE. The OE control signal should be kept inactive (high) during write cycles to avoid bus
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DS1384
contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the outputs in tWEZ from its falling edge. When the address value presented to the DS1384 during the write is in the range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and data will be written into the device. When the address value presented to the DS1384 during the write is in the range of 00040H through 1FFFFH, an external SRAM location will be selected.
DATA RETENTION MODE
When VCCI is within nominal limits (VCC > 4.5V) the DS1384 can be accessed as described above with read or write cycles. However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the internal clock registers and external RAM is blocked from access. This is accomplished internally by inhibiting access to the clock registers via the CE signal. At this time the power fail output signal (PFO) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner by forcing CEO to high level. This level is within 0.2 volts of the VCCI input. CEO will remain at this level as long as VCCI remains at an out-of-tolerance condition. When VCCI falls below the level of the battery (VBAT1 or VBAT2), power input is switched from the VCCI pin to the VBAT pin and the clock registers are maintained from the attached battery supply. External RAM is also powered by the VBAT input when VCCI is below VBAT pin through the VCCO pin. The VCCO pin is capable of supplying 100A of current to the attached memory with less than 0.3V drop under this condition. On power-up, when VCCI returns to in-tolerance conditions, write protection continues for 150ms by inhibiting CEO. The PFO signal also remains active during this time. The DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications which require added reliability or increased battery capacity. When two batteries are used, the higher of the two is selected for use. A selected battery will remain as backup supply until it is significantly below the other. When the selected battery voltage falls below the alternate battery by about 0.6V, the alternate battery is selected and then becomes the backup supply. This switching occurs transparently to the user and continues until both batteries are exhausted. When only a single battery is required, both battery inputs can be connected together. However, a more effective method of using a single battery supply is to ground the unused battery input. When using a single battery, VBAT1 is the preferred input.
WATCHDOG TIMEKEEPER REGISTERS
The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar, Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The Command Register bits are affected by both internal and external functions. This register will be discussed later. The 50 bytes of RAM registers are accessed from the external address and data bus and reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the time of day alarm information. Time of day alarm information is stored in BCD. Register B is the Command Register and information in this register is binary. Register C and D are the Watchdog Alarm Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through register 0003FH are on-chip user bytes and can be used to contain data at the user's discretion.
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Figure 1. DS1384 Block Diagram
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Figure 2. DS1384 Watchdog Timekeeper Registers
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Table 1. Time Of Day Alarm Mask Bits REGISTER MINUTES HOURS 1 1 0 1 0 0 0 0 DAYS 1 1 1 0 DESCRIPTION Alarm Once Per Minute Alarm When Minutes Match Alarm When Hours And Minutes Match Alarm When Hours, Minutes, And Days Match
Note: any other bit combinations of mask bit settings produce illogical operation.
TIME-OF-DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day data in BCD. Ten bits within these eight registers are not used and will always read 0 regardless of how they are written. Bits 6 and 7 in the Months Register (9) are binary bits. When set to logical 0, EOSC (bit 7) enables the real-time clock oscillator. This bit will normally be turned on by the user during device initialization. However, the oscillator can be turned on and off as necessary by setting this bit to the appropriate level. Bit 6 of this same byte controls the square wave output (pin 24). When set to logical 0, the square wave output pin will output a 1024 Hz square wave signal. When set to logic 1 the square wave output pin is in a high impedance state. Bit 6 of the Hours Register is defined as the 12- or 24-Hour Select Bit. When set to logic 1, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/ PM bit with logical one being PM. In the 24hour mode, bit 5 is the second 10-hour bit (20-23 hours). The time of day registers are updated every 0.01 seconds from the real time clock, except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running. The preferred method of synchronizing data access to and from the Watchdog Timekeeper is to access the Command Register by doing a write cycle to address location 0B and setting the TE bit (Transfer Enable bit) to a logic 0. This will freeze the external time of day registers at the present recorded time allowing access to occur without danger of simultaneous update. When the watch registers have been read or written a second write cycle to location 0B, setting the TE bit to a logic 1, will put the time of day registers back to being updated every 0.01 second. No time is lost in the real time clock because the internal copy of the time of day register buffers are continually incremented while the external memory registers are frozen. An alternate method of reading and writing the time of day registers is to ignore synchronization. However, any single read may give erroneous data as the real time clock may be in the process of updating the external memory registers as data is being read. The internal copies of seconds through years are incremented and Time of Day Alarm is checked during the period that hundredths of seconds reads 99 and are transferred to the external register when hundredths of seconds roll from 99 to 00. A way of making sure data is valid is to do multiple reads and compare. Writing the registers can also produce erroneous results for the same reasons. A way of making sure that the write cycle has caused proper update is to do read verifies and re-execute the write cycle if data is not correct. While the possibility of erroneous results from reads and write cycles has been stated, it is worth noting that the probability of an incorrect result is kept to a minimum due to the redundant structure of the Watchdog Timekeeper.
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DS1384
TIME-OF-DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the time of day alarm registers. Bits 3, 4, 5, and 6 of register 7 will always read 0 regardless of how they are written. Bit 7 of registers 3, 5, and 7 are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. An alarm will be generated every day when bit 7 of register 7 is set to a logic 1. Similarly, an alarm is generated every hour when bit 7 of registers 7 and 5 is set to a logic 1. When bit 7 of registers 7, 5, and 3 is set to a logic 1, an alarm will occur every minute when register 1 (seconds) rolls from 59 to 00. Time of day alarm registers are written and read in the same format as the time of day registers. The time of day alarm flag and interrupt is always cleared when alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog Alarm. The two registers contain a time count from 00.01 seconds to 99.99 seconds in BCD. The value written into the Watchdog Alarm Registers can be written or read in any order. Any access to Register C or D will cause the Watchdog Alarm to reinitialize and clears the Watchdog Flag Bit and the Watchdog Interrupt Output. When a new value is entered or the Watchdog Registers are read, the Watchdog Timer will start counting down from the entered value to 0. When 0 is reached, the Watchdog Interrupt Output will go to the active state. The Watchdog Timer Countdown is interrupted and reinitialized back to the entered value every time either of the registers are accessed. In this manner, controlled periodic accesses to the Watchdog Timer can prevent the Watchdog Alarm from ever going to an active level. If access does not occur, countdown alarm will be repetitive. The Watchdog Alarm Registers always read the entered value. The actual count down register is internal and is not readable. Writing registers C and D to 0 will disable the Watchdog Alarm feature.
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The operation of each bit is as follows: Bit 7: TE (Transfer Enable). This bit when set to a logic 0 will disable the transfer of data between internal and external clock registers. The contents in the external clock registers are now frozen and reads or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates. Bit 6: IPSW (Interrupt Switch). When set to a logic 1, INTA is the Time of Day Alarm and INTB/(INTB) is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the Watchdog Alarm output and INTB /(INTB) is the Time of Day Alarm output. Bit 5: IBH/LO (Interrupt B Sink or Source Current). When this bit is set to a logic 1 and VCC is applied, INTB /(INTB) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTB will sink current (see DC characteristics IOL). Bit 4: PU/LVL (Interrupt Pulse Mode or Level Mode). This bit determines whether both interrupts will output a pulse or level signal. When set to a logic 0, INTA and INTB /(INTB) will be in the level mode. When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of 3 ms and then release. INTB /(INTB) will either sink or source current, depending on the condition of bit 5, for a minimum of 3 ms and then release.
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DS1384
Bit 3: WAM (Watchdog Alarm Mask). When this bit is set to a logic 0, the Watchdog Interrupt output will be activated. The activated state is determined by bits 1,4,5, and 6 of the Command Register. When this bit is set to a logic 1, the Watchdog interrupt output is deactivated. Bit 2: TDM (Time-of-Day Alarm Mask). When this bit is set to a logic 0, the Time of Day Alarm Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the Command Register. When this bit is set to a logic 1, the Time of Day Alarm interrupt output is deactivated. Bit 1: WAF (Watchdog Alarm Flag). This bit is set to a logic 1 when a watchdog alarm interrupt occurs. This bit is read-only. The bit is reset when any of the Watchdog Alarm registers are accessed. When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active. Bit 0: TDF (Time-of-Day Flag). This is a read-only bit. This bit is set to a logic 1 when a time of day alarm has occurred. The time the alarm occurred can be determined by reading the Time of Day Alarm registers. This bit is reset to a logic 0 state when any of the Time of Day Alarm registers is accessed. When the interrupt is in the pulse mode (see bit 4 definition), this flag will be in the logic 1 state only during the time the interrupt is active.
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.....................................................-0.3V to +7.0V Operating Temperature Range..........................................................................0C to +70C Storage Temperature Range..........................................................................-20C to +70C Soldering Temperature.................................................See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0C to +70C)
PARAMETER Supply Voltage Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs Battery Input Voltage
SYMBOL VCC VIH VIL VBAT
MIN 4.5 2.0 -0.3 2.4
TYP
MAX 5.5 VCC + 0.3 0.8 4.0V
UNITS V V V V
NOTES 1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to 70C.)
PARAMETER Average VCC PowerSupply Current TTL Standby Current (CE = VIH) CMOS Standby Current (CE < VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current Output Logic 1 Voltage (IOH = -1.0mA) Output Logic 0 Voltage (IOH = +2.1mA) Output Voltage Output Current Write Protection Voltage Output Voltage Output Current Battery Leakage OSC ON Battery Leakage OSC OFF Switchover Voltage
SYMBOL ICC1 ICC2 ICC3 IIL IIO VOH VOL VCCO1 ICCO1 VPF VCCO2 ICCO2 IBAT1 IBAT2 VSO
MIN
TYP 7 2 1
MAX 15 5 3 +1 +1
UNITS mA mA mA A A V
NOTES 2, 3 2, 3 2, 3
1 -1 2.4
0.4 VCC - 0.3 4.0 VBAT -0.3 4.25 85 4.5 100 500 100 VBAT1, VBAT2
V V mA V V A nA nA V 4 4 5 6 6
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AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0C to +70C.)
PARAMETER Read Cycle Time Address Access Time CE Access Time CE Data Off Time Output Enable Access Time Output Enable Data Off Time Output Enable to DQ Low-Z CE to DQ Low-Z Output Hold from Address CE to CEO Low or High OE Low to OER Low A0-A16 00040h OE High to OER High Time Address 00040h-1FFFFh to OER Low Address 00000h-0003Fh to OER High Write Cycle Time Address Setup Time CE Pulse Width Address Hold from End of Write Write Pulse Width CE Data Off Time WE Data Off Time WE or CE Inactive Time Data Setup Time Data Hold Time High INTA and INTB Pulse Width
SYMBOL tRC tACC tCO tCEZ tOE tOEZ tOEL tCEL tOH tCEPD tOERL tRO tAOEL tAOEH tWC tAW tCEW tAH tWP tCEZ tWEZ tWR tDS tDH tIPW
MIN 120
TYP
MAX 120 120 40 60 40
5 10 5 25 20 20 50 40 120 0 120 10 80 40 40 10 45 0 3
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
NOTES
AC TEST CONDITIONS
Input Levels: 0V to 3V Transition Times: 5ns
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CAPACITANCE
(TA = +25C)
PARAMETER Capacitance on All Pins (Except DQ) Capacitance on DQ Pins
SYMBOL CI CDQ
MIN
TYP 7 7
MAX 15 15
UNITS pF pF
NOTES
AC ELECTRICAL CHARACTERISTICS
(TA = 0C to +70C)
PARAMETER CE at VIH before PowerDown VPF (Max) to VPF (Min) VCC Fall Time VPF (Min) to VSO VCC Fall Time VPF (Min) to VPF (Max) VCC Rise Time Power-Up Expected Data Retention Time (Oscillator On)
SYMBOL tPD tF tFB tR tREC tDR
MIN 0 300 10 0 10 10
TYP
MAX
UNITS s s s s
NOTES
150
ms years 7
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READ CYCLE TIMING--RTC AND EXTERNAL SRAM CONTROL SIGNALS
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OER TIMING WHEN SWITCHING BETWEEN LOWER MEMORY (00000h-0003Fh) AND UPPER MEMORY (00040h-1FFFFh)
WRITE CYCLE TIMING--RTC AND EXTERNAL SRAM CONTROL SIGNALS
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POWER-UP TIMING DIAGRAM
POWER-DOWN TIMING DIAGRAM
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INTERRUPT OUTPUTS PULSE MODE TIMING DIAGRAM (See Notes 8 and 9)
NOTES:
1) All voltages are referenced to ground. Typical values are at +25C and nominal supplies. Outputs are open. Value for voltage and currents is from the VCCI input pin to the VCCO pin. Write protection trip point occurs during power fail prior to switchover from VCC to VBAT. Value for voltage and currents is from the VBAT input pin to the VCCO pin. Data retention time depends on the size of battery selected and the amount of current demanded by the static RAM in backup mode. The battery capacity (mA * hr) to achieve a tDR of 10 years is given by the formula: C = (IBAT1 + IRAM) x 24 x 365 x 10, where IRAM is the standby current of the static RAM at the battery voltage. For the DS1384 chip alone, a standard 48mAh lithium cell battery will provide greater than 10 years of data retention in the absence of power. 8) Applies to both interrupt pins when the alarms are set to pulse. 9) Interrupt output occurs within 100ns of the alarm condition existing. 2) 3) 4) 5) 6) 7)
OUTPUT LOAD
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PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2005 Maxim Integrated Products * Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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